Physical Design Engineer Job at NPA Worldwide, Milpitas, CA

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  • NPA Worldwide
  • Milpitas, CA

Job Description

Description

Our customer is an innovative enterprise that designs, develops and delivers System-on-Chip solutions for customers worldwide. The company focuses on AR/VR, ADAS, imaging, networking, data storage and other dynamic technologies that drive today’s leading-edge applications. They combine world-class expertise, experience, and an extensive IP portfolio to provide exceptional solutions and ensure a better quality of experience for customers. Founded in 2015, they headquartered in Yokohama, and has offices in Japan, Asia, United States and Europe to lead its product development and sales activities.

We are seeking a Physical Design Engineer in a hands-on technical position and will have opportunities to work on a variety of challenging designs. Critical to this position is the ability to articulate technical discussions with ASIC Customers and design teams and work closely with customer, frontend and integration teams to ensure successful tape outs. This is a Hybrid opportunity in Milpitas, CA

Primary Responsibilities:

  • Pre-layout STA to ascertain feasibility, timing constraint validation and feedback to customers and design teams
  • Chip/Block Level “Floorplanning” and pin assignment
  • Review top-level/block-level clock specifications for completeness and feasibility
  • Handle all the Physical design tasks (Placement, Timing Optimization, Clock Tree Synthesis, Routing)
  • Perform sign-off tasks (RC Extraction, Static Timing Analysis, IR drop analysis and Physical Verification)
  • Presentations and Customer Interaction in customer meetings

Necessary Qualifications:

  • BSEE, with 5+ years of experience or equivalent experience. MSEE preferred.
  • Experience in ASIC Physical Design; Experience in a SoC product development organization with tape outs at 28nm/16nm design nodes and lower.
  • Hands-on Experience with implementation EDA tools like ICC2/Innovus.
  • Scripting (Perl/Tcl/Python) is required.
  • Good understanding of ASIC frontend design.
  • Experience in both Flat and Hierarchical layouts.
  • Strong problem-solving skills and ability to analyze and resolve physical design issues related to library, timing constraints or CAD tools is required.
  • Experience with power analysis and IR-drop tools (prime power/Redhawk) and Static Timing Analysis (Primetime).
  • Experience with Physical Verification and fix PV errors in layout.
  • Expert handling of Verilog HDL based Netlists, Physical design libraries.
  • Team player with good interpersonal and communication skills; ability to explain processes and answer customer questions during meetings.

Compensation: $170,000 - 210,000 base salary DOE, plus an excellent benefits package.

Applicants must be authorized to work for any U.S. employer.

Staff Smart, Inc. is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, protected veteran status, genetic information, disability status, or any other characteristic protected by law.

Job Tags

Full time, Worldwide,

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